Many 2.5D applications utilize decoupling capacitors. For example, silicon (Si) interposers are implemented by embedding a thin-film parallel plate capacitor in the interposer routing. However, integrated capacitors take up valuable space that could otherwise be used for signal routing in a back-end-of-line (BEOL)/redistribution layer (RDL). An additional drawback is the low capacitance values of such designs. Another conventional method is to utilize capacitors (e.g., ceramic and Si surface mount capacitors) mounted on the surface of the wafer interposer. However, surface-mounted capacitors are typically large and take up valuable space on the surface of the interposer that could be used for die placement. In addition, surface-mounted capacitors must be square/rectangle shaped, which limits the placement of dies on the interposer.
A need therefore exists for a methodology enabling a BEOL/RDL process to fabricate a high-capacitance, low profile capacitor on an interposer surface and the resulting device.